CPC H01L 29/93 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 29/0673 (2013.01); H01L 29/66174 (2013.01)] | 20 Claims |
1. An integrated circuit structure, comprising:
a varactor structure on a semiconductor island on a semiconductor substrate, the varactor structure comprising a plurality of discrete gate stacks on the semiconductor island;
a tap structure adjacent to the varactor structure on the semiconductor island, the tap structure comprising a plurality of merged gate stacks on the semiconductor island; and
a transistor structure on the semiconductor substrate, the transistor structure isolated from the semiconductor island, and the transistor structure comprising a plurality of merged vertical arrangements of horizontal nanowires, and a plurality of gate stacks over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.
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