US 11,869,987 B2
Gate-all-around integrated circuit structures including varactors
Ayan Kar, Portland, OR (US); Saurabh Morarka, Hillsboro, OR (US); Carlos Nieva-Lozano, Beaverton, OR (US); Kalyan Kolluru, Portland, OR (US); Biswajeet Guha, Hillsboro, OR (US); Chung-Hsun Lin, Portland, OR (US); Brian Greene, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 7, 2022, as Appl. No. 17/860,056.
Application 17/860,056 is a division of application No. 16/830,112, filed on Mar. 25, 2020, granted, now 11,417,781.
Prior Publication US 2022/0344519 A1, Oct. 27, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 29/93 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01)
CPC H01L 29/93 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 29/0673 (2013.01); H01L 29/66174 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a varactor structure on a semiconductor island on a semiconductor substrate, the varactor structure comprising a plurality of discrete gate stacks on the semiconductor island;
a tap structure adjacent to the varactor structure on the semiconductor island, the tap structure comprising a plurality of merged gate stacks on the semiconductor island; and
a transistor structure on the semiconductor substrate, the transistor structure isolated from the semiconductor island, and the transistor structure comprising a plurality of merged vertical arrangements of horizontal nanowires, and a plurality of gate stacks over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.