US 11,869,984 B2
Semiconductor device and fabrication method thereof
Lianhong Wang, Hefei (CN); and Er-Xuan Ping, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 13, 2021, as Appl. No. 17/401,317.
Application 17/401,317 is a continuation of application No. PCT/CN2021/103782, filed on Jun. 30, 2021.
Claims priority of application No. 202010887358.6 (CN), filed on Aug. 28, 2020.
Prior Publication US 2022/0069139 A1, Mar. 3, 2022
Int. Cl. H01L 29/861 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/8611 (2013.01) [H01L 29/66128 (2013.01); H01L 29/66136 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a semiconductor structure positioned on a side of the substrate, the semiconductor structure comprising a first semiconductor structure and a second semiconductor structure, the first semiconductor structure and the second semiconductor structure forming a PN junction;
an insulating layer, positioned on a side of the semiconductor structure facing away from the substrate; and
a conductive layer positioned on a side of the insulating layer facing away from the substrate, an orthographic projection of the conductive layer on the substrate at least partially overlapping an orthographic projection of the PN junction on the substrate;
wherein the conductive layer is configured to reduce a potential barrier of the PN junction formed by the first semiconductor structure and the second semiconductor structure;
wherein the conductive layer comprises a first conductive layer and a second conductive layer, the first conductive layer is a polysilicon conductor doped with a P-type ion, and the second conductive layer is a polysilicon conductor doped with an N-type ion.