US 11,869,979 B2
Semiconductor device
Shunpei Yamazaki, Setagaya (JP); Katsuaki Tochibayashi, Isehara (JP); Ryota Hodo, Atsugi (JP); Kentaro Sugaya, Atsugi (JP); and Naoto Yamade, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Apr. 22, 2022, as Appl. No. 17/727,038.
Application 17/727,038 is a continuation of application No. 16/963,928, granted, now 11,316,051, previously published as PCT/IB2019/051397, filed on Feb. 21, 2019.
Claims priority of application No. 2018-040286 (JP), filed on Mar. 7, 2018; and application No. 2018-040287 (JP), filed on Mar. 7, 2018.
Prior Publication US 2022/0246765 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/00 (2006.01); H01L 29/00 (2006.01); H01L 29/786 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H10B 12/00 (2023.01)
CPC H01L 29/7869 (2013.01) [H01L 29/24 (2013.01); H01L 29/66742 (2013.01); H10B 12/05 (2023.02); H10B 12/31 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a transistor, the transistor comprising:
a first insulator;
a second insulator over the first insulator;
a first oxide over the second insulator;
a second oxide over the first oxide;
a third oxide over the second oxide;
a first conductor and a second conductor over the second oxide;
a third insulator over the third oxide; and
a third conductor over the third insulator;
wherein in a channel width direction of the transistor, with reference to a height of a bottom surface of the first insulator, a height of a bottom surface of the third conductor in a region where the third conductor and the second oxide do not overlap with each other is lower than a height of a bottom surface of the second oxide, and
wherein in the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator.