US 11,869,955 B2
Integrated circuit with nanosheet transistors with robust gate oxide
Jia-Ni Yu, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu (TW); Mao-Lin Huang, Hsinchu (TW); Lung-Kun Chu, Hsinchu (TW); Chung-Wei Hsu, Hsinchu (TW); Chih-Hao Wang, Hsinchu (TW); and Kuan-Lun Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 8, 2021, as Appl. No. 17/370,822.
Prior Publication US 2023/0009349 A1, Jan. 12, 2023
Int. Cl. H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 21/8234 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 21/3115 (2006.01); H01L 27/088 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/28185 (2013.01); H01L 21/3115 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 27/0886 (2013.01); H01L 29/0665 (2013.01); H01L 29/513 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A method, comprising:
forming a plurality of first semiconductor nanosheets corresponding to channel regions of a first gate all around transistor;
forming a plurality of second semiconductor nanosheets corresponding to channel regions of a second gate all around transistor;
depositing an interfacial dielectric layer on the first and second semiconductor nanosheets;
depositing a high-K dielectric layer on the interfacial dielectric layer;
depositing a cap layer on the high-K dielectric layer;
removing the cap layer from the high-K dielectric layer on the second semiconductor nanosheets; and
diffusing metal atoms from the cap layer into the interfacial dielectric layer on the first semiconductor nanosheets by performing a thermal annealing process after removing the cap layer from the high-K dielectric layer on the second semiconductor nanosheets.