US 11,869,954 B2
Nanostructured channel regions for semiconductor devices
Chansyun David Yang, Shinchu (TW); Keh-Jeng Chang, Hsinchu (TW); Chan-Lon Yang, Taipei (TW); and Perng-Fei Yuh, Walnut Creek, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 28, 2021, as Appl. No. 17/334,541.
Prior Publication US 2022/0384599 A1, Dec. 1, 2022
Int. Cl. H01L 29/00 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/10 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/1037 (2013.01); H01L 29/401 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on a substrate;
forming a source/drain (S/D) region on the substrate;
forming a nanostructured region through the superlattice structure;
forming a gate structure surrounding the nanostructured region about a first axis and surrounding the first nanostructured layers about a second axis different from the first axis; and
forming contact structures on the S/D region and the gate structure.