US 11,869,953 B2
High voltage transistor device and method for fabricating the same
Sheng-Yao Huang, Kaohsiung (TW); Yu-Ruei Chen, New Taipei (TW); Zen-Jay Tsai, Tainan (TW); and Yu-Hsiang Lin, New Taipei (TW)
Assigned to UNITED MICROELECTRONICS CORP, Hsinchu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsinchu (TW)
Filed on Sep. 13, 2022, as Appl. No. 17/943,654.
Application 17/943,654 is a division of application No. 17/213,868, filed on Mar. 26, 2021, granted, now 11,476,343.
Claims priority of application No. 202110086666.3 (CN), filed on Jan. 22, 2021.
Prior Publication US 2023/0006048 A1, Jan. 5, 2023
Int. Cl. H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01)
CPC H01L 29/42364 (2013.01) [H01L 21/28238 (2013.01); H01L 29/0653 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A method for fabricating a high-voltage transistor device, comprising:
providing a semiconductor substrate;
etching a portion of the semiconductor substrate using a first patterned mask to form a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile;
forming an isolation structure, on an outside of the plurality of grooves, and extending from the surface downwards into the semiconductor substrate to defining a high-voltage area;
etching another portion of the semiconductor substrate in the high-voltage area using a second patterned mask;
forming a gate dielectric layer, on the high-voltage area and partially filled in the plurality of grooves and contacting to a bottom of the plurality of grooves;
forming a gate, on the gate dielectric layer;
forming a source region, in the semiconductor substrate; and
forming a drain region, in the semiconductor substrate and isolated from the source region.