US 11,869,952 B2
Semiconductor structure and method for forming same
Kang You, Hefei (CN); and Jie Bai, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jul. 27, 2021, as Appl. No. 17/386,474.
Application 17/386,474 is a continuation of application No. PCT/CN2021/079667, filed on Mar. 9, 2021.
Claims priority of application No. 202010230470.2 (CN), filed on Mar. 27, 2020.
Prior Publication US 2021/0359094 A1, Nov. 18, 2021
Int. Cl. H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/4236 (2013.01) [H01L 21/02057 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/66621 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
providing a substrate;
forming an active region on the substrate;
forming at least one trench in the active region, the at least one trench at least dividing the active region into a source region on one side of the at least one trench and a drain region on another side of the at least one trench;
forming a gate structure in the at least one trench; and
forming an elevated source region and an elevated drain region on the source region and the drain region, respectively;
wherein a bottom width of the elevated source region is equal to a top width of the source region, and a bottom width of the elevated drain region is equal to a top width of the drain region;
a top width of the elevated source region is greater than the bottom width of the elevated source region, and a top width of the elevated drain region is greater than the bottom width of the elevated drain region, and an opening size of the at least one trench is greater than the bottom width of the elevated source region or the bottom width of the elevated drain region.