US 11,869,939 B2
Integration methods to fabricate internal spacers for nanowire devices
Seiyon Kim, Portland, OR (US); Kelin J. Kuhn, Aloha, OR (US); Tahir Ghani, Portland, OR (US); Anand S. Murthy, Portland, OR (US); Mark Armstrong, Portland, OR (US); Rafael Rios, Portland, OR (US); Abhijit Jayant Pethe, Hillsboro, OR (US); and Willy Rachmady, Beaverton, OR (US)
Assigned to Sony Group Corporation, Tokyo (JP)
Filed by Sony Group Corporation, Tokyo (JP)
Filed on Mar. 24, 2022, as Appl. No. 17/703,218.
Application 15/333,123 is a division of application No. 13/539,195, filed on Jun. 29, 2012, granted, now 9,484,447, issued on Nov. 1, 2016.
Application 17/703,218 is a continuation of application No. 17/013,449, filed on Sep. 4, 2020, granted, now 11,302,777.
Application 17/013,449 is a continuation of application No. 16/740,132, filed on Jan. 10, 2020, granted, now 10,804,357, issued on Oct. 13, 2020.
Application 16/740,132 is a continuation of application No. 16/358,613, filed on Mar. 19, 2019, granted, now 10,580,860, issued on Jul. 11, 2019.
Application 16/358,613 is a continuation of application No. 16/153,456, filed on Oct. 5, 2018, granted, now 10,283,589, issued on May 7, 2019.
Application 16/153,456 is a continuation of application No. 15/859,226, filed on Dec. 29, 2017, granted, now 10,121,856, issued on Nov. 6, 2018.
Application 15/859,226 is a continuation of application No. 15/333,123, filed on Oct. 24, 2016, granted, now 9,859,368, issued on Jan. 2, 2018.
Prior Publication US 2022/0262901 A1, Aug. 18, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 21/306 (2006.01); H01L 21/3105 (2006.01); H01L 21/3115 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); B82Y 40/00 (2011.01)
CPC H01L 29/0673 (2013.01) [H01L 21/30604 (2013.01); H01L 21/3105 (2013.01); H01L 21/31155 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/78 (2013.01); H01L 29/78696 (2013.01); B82Y 40/00 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a nanowire stack disposed above a substrate, the nanowire stack including vertically-stacked nanowires;
a gate structure wrapped around each of the nanowires to define a channel region of the device, the gate structure including gate sidewalls;
a pair of source/drain regions on opposite sides of the channel region;
a first internal spacer arranged along at least a portion of one of the gate sidewalls between two adjacent ones of the nanowires; and
second internal spacers arranged along respective gate sidewalls underneath a bottommost nanowire in the nanowire stack.