US 11,869,930 B2
Method for forming semiconductor structure and semiconductor structure
Yong Lu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jul. 8, 2021, as Appl. No. 17/370,313.
Application 17/370,313 is a continuation of application No. PCT/CN2021/077837, filed on Feb. 25, 2021.
Claims priority of application No. 202010181067.5 (CN), filed on Mar. 16, 2020.
Prior Publication US 2021/0335993 A1, Oct. 28, 2021
Int. Cl. H01L 49/02 (2006.01); H01L 21/3213 (2006.01); H10B 12/00 (2023.01)
CPC H01L 28/91 (2013.01) [H01L 21/32139 (2013.01); H01L 28/92 (2013.01); H10B 12/03 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
forming a stacked structure on a surface of a substrate, capacitor contacts being arranged in the substrate, and the stacked structure comprising supporting layers and sacrificial layers which are alternately stacked along a direction perpendicular to the substrate wherein the forming the stacked structure on the surface of the substrate comprises:
providing the substrate; and
depositing a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer, and a third supporting layer in sequence along the direction perpendicular to the substrate;
forming a buffer layer on a surface of the third supporting layer facing away from the substrate;
forming capacitor holes penetrating through the stacked structure and the buffer layer and exposing the capacitor contacts;
forming a first electrode layer covering side walls and bottom walls of the capacitor holes and a surface of the buffer layer facing away from the third supporting layer and contacting with the capacitor contacts;
forming a mask layer on a surface of the first electrode layer which is located on the surface of the buffer layer facing away from the third supporting layer, such that the capacitor holes are sealed, wherein an etching pattern exposing the first electrode layer is arranged in the mask layer;
forming an etching window penetrating through the buffer layer and exposing the third supporting layer, by etching the first electrode layer and the buffer layer in sequence along the etching pattern;
removing part of the supporting layers and all of the sacrificial layers in the stacked structure along the etching window;
removing the buffer layer after the removing part of the supporting layers and all of the sacrificial layers such that the first electrode layer protrudes over a residual stacked structure; and
forming a dielectric layer covering the surface of the first electrode layer and a surface of the residual stacked structure, and a second electrode layer covering a surface of the dielectric layer, to form a capacitor.