US 11,869,927 B2
Method of manufacturing semiconductor device
Yumiko Kawano, Nirasaki (JP); Genji Nakamura, Nirasaki (JP); Philippe Gaubert, Nirasaki (JP); and Hajime Nakabayashi, Nirasaki (JP)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Appl. No. 17/279,830
Filed by Tokyo Electron Limited, Tokyo (JP)
PCT Filed Sep. 19, 2019, PCT No. PCT/JP2019/036690
§ 371(c)(1), (2) Date Mar. 25, 2021,
PCT Pub. No. WO2020/066819, PCT Pub. Date Apr. 2, 2020.
Claims priority of application No. 2018-183304 (JP), filed on Sep. 28, 2018.
Prior Publication US 2021/0399085 A1, Dec. 23, 2021
Int. Cl. H01L 21/02 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/56 (2013.01) [H01L 21/022 (2013.01); H01L 21/0228 (2013.01); H01L 21/02181 (2013.01); H01L 21/02189 (2013.01); H01L 21/02321 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
a first laminating step of laminating a first electrode film on a substrate;
a second laminating step of laminating a capacitive insulator on the first electrode film;
a third laminating step of laminating a metal oxide on the capacitive insulator;
a first annealing step of annealing the first electrode film, the capacitive insulator, and the metal oxide, which are laminated on the substrate; and
a fourth laminating step of laminating a second electrode film on the annealed metal oxide,
wherein the capacitive insulator is an oxide that contains at least one of zirconium and hafnium,
wherein the metal oxide is an oxide that contains at least one of tungsten, molybdenum, and vanadium, and
wherein the first annealing step is performed after the third laminating step and before the fourth laminating step.