US 11,869,894 B2
Metallization structures for stacked device connectivity and their methods of fabrication
Aaron D. Lilak, Beaverton, OR (US); Anh Phan, Beaverton, OR (US); Patrick Morrow, Portland, OR (US); Willy Rachmady, Beaverton, OR (US); Gilbert Dewey, Beaverton, OR (US); Jessica M. Torres, Portland, OR (US); Kimin Jun, Portland, OR (US); Tristan A. Tronic, Aloha, OR (US); Christopher J. Jezewski, Portland, OR (US); Hui Jae Yoo, Hillsboro, OR (US); Robert S. Chau, Beaverton, OR (US); and Chi-Hwa Tsang, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 13, 2022, as Appl. No. 17/864,264.
Application 17/864,264 is a continuation of application No. 16/957,047, granted, now 11,430,814, previously published as PCT/US2018/020945, filed on Mar. 5, 2018.
Prior Publication US 2022/0344376 A1, Oct. 27, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/84 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC H01L 27/1207 (2013.01) [H01L 21/02532 (2013.01); H01L 21/28568 (2013.01); H01L 21/845 (2013.01); H01L 27/1211 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/41791 (2013.01); H01L 29/45 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H10B 61/22 (2023.02); H10B 63/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a first device structure comprising:
a first body of semiconductor material comprising at least one of silicon or germanium; and
a plurality of terminals coupled with the first body; and
an insulator layer between the first device structure and an underlying second device structure, wherein the insulator layer comprises silicon and oxygen, and wherein the second device structure comprises:
a second body of semiconductor material comprising at least one of silicon or germanium;
a gate electrode coupled to the second body;
a spacer adjacent to a sidewall of the gate electrode;
a source or drain material coupled with the second body and between at least a portion of the spacer and the insulator layer, wherein the source or drain material comprises at least one of silicon or germanium and one or more donor or acceptor impurities, and;
a metallization structure in contact with the source or drain material, wherein the metallization structure extends through a thickness of the insulator layer and is coupled with one of the terminals of the first device structure.