US 11,869,889 B2
Self-aligned gate endcap (SAGE) architectures without fin end gap
Szuya S. Liao, Portland, OR (US); Scott B. Clendenning, Portland, OR (US); Jessica Torres, Portland, OR (US); Lukas Baumgartel, Portland, OR (US); Kiran Chikkadi, Hillsboro, OR (US); Diane Lancaster, Hillsboro, OR (US); Matthew V. Metz, Portland, OR (US); Florian Gstrein, Portland, OR (US); Martin M. Mitan, Beaverton, OR (US); and Rami Hourani, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2019, as Appl. No. 16/579,055.
Prior Publication US 2021/0091075 A1, Mar. 25, 2021
Int. Cl. H01L 23/535 (2006.01); H01L 27/088 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 23/538 (2006.01); H01L 27/092 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/76229 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 27/0924 (2013.01); H01L 21/823462 (2013.01); H01L 21/823871 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a semiconductor fin having a cut along a longest length of the semiconductor fin in a plan view perspective, the cut between a first portion of the semiconductor fin and a second portion of the semiconductor fin, the first portion of the semiconductor fin along a same axis as the second portion of the semiconductor fin in the plan view perspective; and
a gate endcap isolation structure having a first portion parallel with the longest length of the semiconductor fin and laterally spaced apart from the first portion of the semiconductor fin, laterally spaced apart from the second portion of the semiconductor fin, and laterally spaced apart from the cut, and the gate endcap isolation structure having a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.