US 11,869,854 B2
Semiconductor structure formed with inductance elements
Chien-Ming Lai, Tainan (TW); Hui-Ling Chen, Kaohsiung (TW); and Zhi-Rui Sheng, Singapore (SG)
Assigned to UNITED MICROELECTRONICS CORPORATION, Hsinchu (TW)
Filed by UNITED MICROELECTRONICS CORPORATION, Hsinchu (TW)
Filed on Jan. 27, 2021, as Appl. No. 17/159,181.
Claims priority of application No. 202011457034.5 (CN), filed on Dec. 11, 2020.
Prior Publication US 2022/0189888 A1, Jun. 16, 2022
Int. Cl. H01L 23/64 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/645 (2013.01) [H01L 23/5227 (2013.01); H01L 24/94 (2013.01); H01L 24/80 (2013.01); H01L 24/83 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48139 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first semiconductor wafer, comprising a first semiconductor substrate and a first inductance layer, wherein the first inductance layer is disposed on the first semiconductor substrate, one side of the first inductance layer away from the first semiconductor substrate has a first bonding surface, the first inductance layer comprises at least one first metal trace, at least one first interconnect structure and a first insulating layer, the first insulating layer covers the at least one first metal trace, and the at least one first interconnect structure is embedded in the first insulating layer and electrically connected to the at least one first metal trace; and
a second semiconductor wafer, comprising a second semiconductor substrate and a second inductance layer, wherein the second inductance layer is disposed on the second semiconductor substrate, one side of the second inductance layer away from the second semiconductor substrate has a second bonding surface, the second inductance layer comprises at least one second metal trace, at least one second interconnect structure and a second insulating layer, the second insulating layer covers the at least one second metal trace, and the at least one second interconnect structure is embedded in the second insulating layer and electrically connected to the at least one second metal trace,
wherein, the first semiconductor wafer and the second semiconductor wafer are coupled to each other, the first bonding surface of the first inductance layer is bonded to the second bonding surface of the second inductance layer, the first insulating layer on the first bonding surface and the second insulating layer on the second bonding surface form a first bond, and the at least one first interconnect structure on the first bonding surface and the at least one second interconnect structure on the second bonding surface form a second bond,
wherein the at least one first metal trace has an input terminal and a first terminal, the at least one second metal trace corresponds to the at least one first metal trace, and the at least one second metal trace has a connection terminal and a second terminal,
wherein the at least one first interconnect structure is electrically connected to the first terminal, the at least one second interconnect structure is electrically connected to the connection terminal, the second bond is formed by the at least one second interconnect structure and the at least one first interconnect structure, and the at least one first metal trace, the at least one first interconnect structure, the at least one second metal trace and the at least one second interconnect structure form a continuous and non-intersecting path between the input terminal and the second terminal and constitute an inductance element.