US 11,869,845 B2
Semiconductor package device and semiconductor wiring substrate thereof
Sheng-Fan Yang, Hsinchu (TW); Wei-Chiao Wang, Hsinchu (TW); and Yi-Tzeng Lin, Hsinchu (TW)
Assigned to GLOBAL UNICHIP CORPORATION, Hsinchu (TW); and TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by GLOBAL UNICHIP CORPORATION, Hsinchu (TW); and TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 29, 2022, as Appl. No. 17/823,063.
Claims priority of application No. 111119707 (TW), filed on May 26, 2022.
Prior Publication US 2023/0387030 A1, Nov. 30, 2023
Int. Cl. H01L 23/52 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 23/498 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/5386 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/552 (2013.01); H01L 25/0652 (2013.01); H01L 24/16 (2013.01); H01L 2224/16235 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor wiring substrate, comprising:
a first circuit layer comprising a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces;
a second circuit layer comprising a plurality of second signal traces and a plurality of second ground traces, wherein the second signal traces and the second ground traces are alternatively arranged on the second circuit layer; and
a first dielectric layer between the first circuit layer and the second circuit layer and having a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.