US 11,869,842 B2
Scalable high speed high bandwidth IO signaling package architecture and method of making
Sanka Ganesan, Chandler, AZ (US); Robert L. Sankman, Phoenix, AZ (US); Arghya Sain, Chandler, AZ (US); Sri Chaitra Jyotsna Chavali, Chandler, AZ (US); Lijiang Wang, Chandler, AZ (US); and Cemil Geyik, Gilbert, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 24, 2019, as Appl. No. 16/521,435.
Prior Publication US 2021/0028116 A1, Jan. 28, 2021
Int. Cl. H01L 23/538 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/5381 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
a package substrate, wherein the package substrate comprises a first routing architecture;
a first die on the package substrate;
a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate; and
a routing patch on the package substrate, wherein the routing patch is a discrete component coupled to a same side of the package substrate as the second die and is laterally spaced apart from the second die, wherein the routing patch is electrically coupled to the second die by a trace in the package substrate, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.