US 11,869,833 B2
Package comprising a substrate with a via interconnect coupled to a trace interconnect and method of fabricating the same
Kun Fang, San Diego, CA (US); Jaehyun Yeon, San Diego, CA (US); Suhyung Hwang, Rancho Mission Viejo, CA (US); and Hyunchul Cho, Suwon (KR)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 15, 2021, as Appl. No. 17/476,383.
Prior Publication US 2023/0078231 A1, Mar. 16, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49822 (2013.01) [H01L 21/4857 (2013.01); H01L 23/49838 (2013.01); H01L 23/3128 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A package comprising:
a substrate comprising:
a plurality of interconnects comprising:
a first via interconnect that includes a first width and
a first trace interconnect directly coupled to a side portion of the first via interconnect;
a second trace interconnect directly coupled to a first surface of the first via interconnect;
wherein the first trace interconnect includes a second width that is less than the first width and the second trace interconnect includes a third width that is less than the first width;
at least one dielectric layer at least partially surrounding the plurality of interconnects; and
an integrated device coupled to the substrate and located over the substrate, wherein the at least one dielectric layer and the plurality of interconnects are located in planes underneath the integrated device.