US 11,869,831 B2
Semiconductor package with improved board level reliability
Chin-Chiang Chang, Hsinchu (TW); Yin-Fa Chen, Hsinchu (TW); and Shih-Chin Lin, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsin-Chu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/460,352.
Claims priority of provisional application 63/089,064, filed on Oct. 8, 2020.
Claims priority of provisional application 63/167,697, filed on Mar. 30, 2021.
Claims priority of provisional application 63/185,394, filed on May 7, 2021.
Prior Publication US 2022/0115303 A1, Apr. 14, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49541 (2013.01) [H01L 23/3107 (2013.01); H01L 23/49503 (2013.01); H01L 24/48 (2013.01); H01L 2224/48175 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a die attach pad;
a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package;
a semiconductor die mounted on the die attach pad;
a molding compound encapsulating the plurality of lead terminals and the semiconductor die; and
at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals, wherein the at least one dummy lead disposed in the corner region is kept a predetermined distance away from adjacent two side edges of the semiconductor package, and therefore does not have an exposed end surface on any of the adjacent two side edges.