US 11,869,829 B2
Semiconductor device with through-mold via
Dong Joo Park, Seoul (KR); Jin Seong Kim, Seoul (KR); Ki Wook Lee, Seoul (KR); Dae Byoung Kang, Kyunggi-do (KR); Ho Choi, Seoul (KR); Kwang Ho Kim, Kyunggi-do (KR); Jae Dong Kim, Seoul (KR); Yeon Soo Jung, Seoul (KR); and Sung Hwan Cho, Kyunggi-do (KR)
Assigned to Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed by Amkor Technology Singapore Holding Pte. Ltd, Valley Point (SG)
Filed on Jul. 10, 2020, as Appl. No. 16/925,599.
Application 16/925,599 is a division of application No. 16/025,465, filed on Jul. 2, 2018, granted, now 10,811,341.
Application 16/025,465 is a division of application No. 15/390,568, filed on Dec. 26, 2016, abandoned.
Application 15/390,568 is a division of application No. 12/348,813, filed on Jan. 5, 2009, abandoned.
Prior Publication US 2020/0343163 A1, Oct. 29, 2020
Int. Cl. H01L 23/482 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 23/48 (2006.01); H01L 23/31 (2006.01); H01L 25/03 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/482 (2013.01) [H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 24/73 (2013.01); H01L 25/03 (2013.01); H01L 25/0657 (2013.01); H01L 25/10 (2013.01); H01L 23/5389 (2013.01); H01L 24/16 (2013.01); H01L 24/24 (2013.01); H01L 24/32 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/244 (2013.01); H01L 2224/24227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/92224 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/19107 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate having a top major surface and a bottom major surface opposite to the top major surface;
an electrically conductive pattern adjoining the top major surface;
conductive lands adjoining the bottom major surface and including a first conductive land, a second conductive land, a third conductive land, and a fourth conductive land;
conductive vias within the substrate and connecting part of the electrically conductive pattern to the conductive lands, the conductive vias including a first conductive via having a first width in a cross-sectional view and connected to the third conductive land;
conductive bumps;
a first semiconductor die mounted to the first conductive land and the second conductive land with the conductive bumps;
an electronic component electrically connected to the electrically conductive pattern of the substrate and mounted on the top major surface of the substrate;
a first package body encapsulating the first semiconductor die and comprising a bottom exterior surface distal to the bottom major surface of the substrate;
a second package body encapsulating the electronic component;
a first electrically conductive path physically and electrically connected to the third conductive land and extending to the bottom exterior surface of the first package body having a second width in the cross-sectional view that is greater than the first width; and
a second electrically conductive path physically and electrically connected to the fourth conductive land and extending to the bottom exterior surface of the first package body, wherein:
the first electrically conductive path comprises a first outer surface exposed from the bottom exterior surface of the first package body and configured as a first external electrical interconnect structure; and
the second electrically conductive path comprises a second outer surface exposed from the bottom exterior surface of the first package body and configured as a second external electrical interconnect structure.