US 11,869,827 B2
Three-dimensional capacitor-inductor based on high functional density through silicon via structure and preparation method thereof
Wei Zhang, Shanghai (CN); Ziyu Liu, Shanghai (CN); Lin Chen, Shanghai (CN); and Qingqing Sun, Shanghai (CN)
Assigned to Shanghai Integrated Circuit Manufacturing Innovation Center Co., Ltd., Shanghai (CN)
Appl. No. 17/052,847
Filed by FUDAN UNIVERSITY, Shanghai (CN); and SHANGHAI INTEGRATED CIRCUIT MANUFACTURING INNOVATION CENTER CO., LTD, Shanghai (CN)
PCT Filed Jul. 2, 2020, PCT No. PCT/CN2020/099976
§ 371(c)(1), (2) Date Mar. 23, 2021,
PCT Pub. No. WO2021/253512, PCT Pub. Date Dec. 23, 2021.
Claims priority of application No. 202010561660.2 (CN), filed on Jun. 18, 2020.
Prior Publication US 2023/0115796 A1, Apr. 13, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 27/01 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01); H01L 27/01 (2013.01); H01L 24/05 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05684 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure, comprising:
a substrate formed with a through silicon via;
a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer, and a second metal layer; and
a three-dimensional inductor, composed center-filled metal of the through silicon via and planar thick metal rewiring,
wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor.