US 11,869,819 B2
Integrated circuit component and package structure having the same
Tzuan-Horng Liu, Taoyuan (TW); Chao-Hsiang Yang, Hsinchu (TW); Hsien-Wei Chen, Hsinchu (TW); and Ming-Fa Chen, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 22, 2022, as Appl. No. 17/870,871.
Application 16/596,758 is a division of application No. 16/016,662, filed on Jun. 25, 2018, granted, now 10,483,174, issued on Nov. 19, 2019.
Application 17/870,871 is a continuation of application No. 17/207,736, filed on Mar. 21, 2021, granted, now 11,450,579.
Application 17/207,736 is a continuation of application No. 16/596,758, filed on Oct. 9, 2019, granted, now 10,957,610, issued on Mar. 23, 2021.
Prior Publication US 2022/0359315 A1, Nov. 10, 2022
Int. Cl. H01L 21/66 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01)
CPC H01L 22/32 (2013.01) [H01L 23/3157 (2013.01); H01L 23/49822 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 2224/0217 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05556 (2013.01); H01L 2224/06515 (2013.01); H01L 2224/13007 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit component, comprising:
a semiconductor substrate;
conductive pads, disposed on and electrically coupled to the semiconductor substrate, and each having a contact region and a testing region next to the contact region, wherein a surface roughness of a surface of the testing region of the at least one of the conductive pads is greater than a surface roughness of a surface of a respective one of the contact regions;
a passivation layer, disposed on the semiconductor substrate, wherein the testing regions and the contact regions of the conductive pads are exposed by the passivation layer;
a post-passivation layer, disposed on the semiconductor substrate, wherein the testing regions of the conductive pads exposed by the passivation layer are covered by the post-passivation layer, and the contact regions of the conductive pads exposed by the passivation layer are exposed by the post-passivation layer; and
conductive vias, respectively disposed on the contact regions of the conductive pads.