CPC H01L 21/76229 (2013.01) [H01L 29/0649 (2013.01)] | 20 Claims |
1. A semiconductor manufacturing method, comprising:
providing a substrate having a plurality of first trenches, wherein a first pattern is formed between two adjacent first trenches;
depositing a first dielectric layer onto the substrate, the first dielectric layer covering at least one side wall of the first pattern;
depositing a second dielectric layer onto the substrate, the second dielectric layer filling the first trenches;
severing the first pattern to form a second pattern on the substrate, wherein severing the first pattern to form the second pattern comprises etching a plurality of second trenches on the first pattern to cut each of the first pattern into the second pattern; and
removing the second dielectric layer from the first trenches.
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