US 11,869,801 B2
Semiconductor manufacturing method
Zhan Ying, Hefei (CN); Qiang Zhang, Hefei (CN); and Yiming Zhu, Hefei (CN)
Assigned to Changxin Memory Technologies, Inc., Hefei (CN)
Filed by Changxin Memory Technologies, Inc., Anhui (CN)
Filed on Aug. 20, 2021, as Appl. No. 17/408,256.
Application 17/408,256 is a continuation of application No. PCT/CN2021/083131, filed on Mar. 26, 2021.
Claims priority of application No. 202010428539.2 (CN), filed on May 20, 2020.
Prior Publication US 2021/0384067 A1, Dec. 9, 2021
Int. Cl. H01L 29/00 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01)
CPC H01L 21/76229 (2013.01) [H01L 29/0649 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor manufacturing method, comprising:
providing a substrate having a plurality of first trenches, wherein a first pattern is formed between two adjacent first trenches;
depositing a first dielectric layer onto the substrate, the first dielectric layer covering at least one side wall of the first pattern;
depositing a second dielectric layer onto the substrate, the second dielectric layer filling the first trenches;
severing the first pattern to form a second pattern on the substrate, wherein severing the first pattern to form the second pattern comprises etching a plurality of second trenches on the first pattern to cut each of the first pattern into the second pattern; and
removing the second dielectric layer from the first trenches.