US 11,869,783 B2
Optimizating semiconductor binning by feed-forward process adjustment
Benjamin D. Briggs, Waterford, NY (US); Lawrence A. Clevenger, Dutchess, NY (US); Nicholas A. Lanzillo, Troy, NY (US); Michael Rizzolo, Albany, NY (US); Theodorus E. Standaert, Clifton Park, NY (US); and James Stathis, Poughquag, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Apr. 29, 2021, as Appl. No. 17/244,084.
Application 17/244,084 is a continuation of application No. 15/791,451, filed on Oct. 24, 2017, granted, now 11,049,744.
Prior Publication US 2021/0249288 A1, Aug. 12, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/67 (2006.01); G06N 5/04 (2023.01); G06N 20/00 (2019.01)
CPC H01L 21/67271 (2013.01) [G06N 5/04 (2013.01); G06N 20/00 (2019.01)] 25 Claims
OG exemplary drawing
 
1. A method for generating a machine learning model for improving performance levels of semiconductor devices during fabrication, the method comprising:
determining, by one or more processors, a first set of correlations between process parameters applied to a metallization layer process of semiconductor device fabrication and data from measurement and test operations performed subsequent to the metallization layer of the semiconductor devices, for a plurality of metallization layers performed during fabrication of a plurality of semiconductor devices;
determining, by one or more processors, a second set of correlations between the data from measurement and test operations performed subsequent to the metallization layer of the semiconductor devices and predicted performance level of the semiconductor devices;
generating a machine learning model, based on the first set of correlations and the second set of correlations; and
training the machine learning model to:
determine an initial sorting bin, a target soring bin, and a current sorting bin of a first semiconductor device, and
determine adjustments to process parameters of a subsequent metallization layer that improve the performance levels of the first semiconductor device by compensating for performance-reducing conditions detected by prior process measurement and testing operations.