US 11,869,725 B2
Multi-stacked capacitor
Michael Hans Enzelberger-Heim, Munich (DE); and Jonas Höhenberger, Kissing (DE)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Nov. 30, 2021, as Appl. No. 17/537,626.
Prior Publication US 2023/0170153 A1, Jun. 1, 2023
Int. Cl. H01G 4/40 (2006.01); H01G 4/008 (2006.01); H01G 4/30 (2006.01)
CPC H01G 4/40 (2013.01) [H01G 4/008 (2013.01); H01G 4/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A stacked capacitor, comprising:
a capacitor stack including:
a base plate having a first surface and a second opposing surface,
a first dielectric layer on or over the base plate,
a first conductive plate on or over the first dielectric layer,
a second dielectric layer on or over the first conductive plate, and
a second conductive plate on or over the second dielectric layer, wherein:
the capacitor stack has a sloped side sloped with respect to the second surface of the base plate;
an insulating layer over the capacitor stack and the sloped side; and
a plurality of vias through the insulating layer to the capacitor stack, including a first via that connects to a portion of the first conductive plate exposed at the sloped side and a second via that connects to a portion of the second conductive plate exposed at the sloped side.