US 11,869,628 B2
Apparatuses and methods to perform low latency access of a memory
Yuan He, Boise, ID (US); and Daigo Toyama, Kanagawa (JP)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jul. 1, 2022, as Appl. No. 17/810,520.
Application 17/810,520 is a continuation of application No. 17/003,913, filed on Aug. 26, 2020, granted, now 11,380,376, issued on Jul. 5, 2022.
Prior Publication US 2022/0335995 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/00 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1039 (2013.01); G11C 7/1045 (2013.01); G11C 7/1096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array;
a register circuit; and
a control circuit configured to selectively provide command and address information including a row and column address to the memory array in response to a low latency mode being disabled and to provide the command and address information including the row and column address to the register circuit in response to the low latency mode being enabled.