CPC G11C 7/222 (2013.01) [G11C 7/1039 (2013.01); G11C 7/1045 (2013.01); G11C 7/1096 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a memory array;
a register circuit; and
a control circuit configured to selectively provide command and address information including a row and column address to the memory array in response to a low latency mode being disabled and to provide the command and address information including the row and column address to the register circuit in response to the low latency mode being enabled.
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