US 11,869,616 B2
Centrally logging and aggregating miscompares on chip during memory test
Senwen Kan, Austin, TX (US); Andrew Payne, Austin, TX (US); Jeffrey W Gossett, Bothell, WA (US); Michael Joseph Pluhta, Seattle, WA (US); Richard A Rodell, Jr., Eagan, MN (US); and Bjarni Benjaminsson, Seattle, WA (US)
Assigned to Cypress Semiconductor Corporation, San Jose, CA (US)
Filed by Cypress Semiconductor Corporation, San Jose, CA (US)
Filed on Nov. 11, 2021, as Appl. No. 17/524,039.
Prior Publication US 2023/0142759 A1, May 11, 2023
Int. Cl. G11C 29/42 (2006.01); G11C 29/44 (2006.01); H03K 19/21 (2006.01); G11C 29/08 (2006.01); G11C 29/18 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/18 (2013.01); G11C 29/4401 (2013.01); H03K 19/21 (2013.01); G11C 2029/4402 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm;
generating, by the BIST unit, miscompare results responsive to performing the memory test on the one or more memory banks of the memory device;
determining, by the BIST unit, failure diagnostic information based on the miscompare results;
generating, by the BIST unit, an error packet comprising the failure diagnostic information and the miscompare results;
determining, by the BIST unit, that the first algorithm was used to perform the memory test associated with the error packet;
tagging, by the BIST unit, the error packet with an identifier to the first algorithm to generate a tagged error packet; and
placing, by the BIST unit, the tagged error packet in a queue of a plurality of error packets to generate a queued error packet.