US 11,869,596 B2
Memory system including a semiconductor memory having a memory cell and a write circuit configured to write data to the memory cell
Suguru Nishikawa, Osaka (JP); Yoshihisa Kojima, Kawasaki (JP); Riki Suzuki, Yokohama (JP); Masanobu Shirakawa, Chigasaki (JP); and Toshikatsu Hida, Yokohama (JP)
Assigned to Kioxia Corporation, Minato-ku (JP)
Filed by Kioxia Corporation, Minato-ku (JP)
Filed on Mar. 6, 2023, as Appl. No. 18/117,520.
Application 18/117,520 is a continuation of application No. 17/849,062, filed on Jun. 24, 2022, granted, now 11,657,875.
Application 17/849,062 is a continuation of application No. 17/027,041, filed on Sep. 21, 2020, granted, now 11,410,729, issued on Aug. 9, 2022.
Application 17/027,041 is a continuation of application No. 16/129,157, filed on Sep. 12, 2018, granted, now 10,818,358, issued on Oct. 27, 2020.
Claims priority of application No. 2017-183074 (JP), filed on Sep. 22, 2017; and application No. 2018-033796 (JP), filed on Feb. 27, 2018.
Prior Publication US 2023/0207016 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 29/02 (2006.01); G11C 29/42 (2006.01); G11C 16/32 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/10 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/32 (2013.01); G11C 16/349 (2013.01); G11C 16/3459 (2013.01); G11C 16/3495 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/42 (2013.01); G11C 11/5671 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device connectable to a controller, the memory device comprising:
at least a first memory cell configured to be programmed to store data corresponding to a threshold voltage of the first memory cell, the first memory cell being configured to store first data in a case where the threshold voltage of the first memory cell is higher than a first reference voltage; and
a peripheral circuit configured to:
write the first data to the first memory cell in a first programming operation by:
applying a first program voltage to the first memory cell in a plurality of first loops;
obtaining a value of a first write parameter by comparing the threshold voltage of the first memory cell with a second reference voltage, the second reference voltage being lower than the first reference voltage; and
verifying that the first data is stored in the first memory cell by comparing the threshold voltage of the first memory cell with the first reference voltage; and
output the value of the first write parameter to the controller.