US 11,869,591 B2
3D memory devices and structures with control circuits
Zvi Or-Bach, Haifa (IL); Jin-Woo Han, San Jose, CA (US); and Brian Cronquist, Klamath Falls, OR (US)
Assigned to Monolithic 3D Inc., Klamath Falls, OR (US)
Filed by Monolithic 3D Inc., Klamath Falls, OR (US)
Filed on Aug. 28, 2023, as Appl. No. 18/239,117.
Application 18/239,117 is a continuation in part of application No. 18/206,040, filed on Jun. 5, 2023, granted, now 11,812,620.
Application 18/206,040 is a continuation in part of application No. 18/105,856, filed on Feb. 5, 2023, granted, now 11,711,928, issued on Jul. 25, 2023.
Application 18/105,856 is a continuation in part of application No. 17/949,988, filed on Sep. 21, 2022, granted, now 11,621,240, issued on Apr. 4, 2023.
Application 17/949,988 is a continuation in part of application No. 17/712,875, filed on Apr. 4, 2022, granted, now 11,482,541, issued on Oct. 25, 2022.
Application 17/712,875 is a continuation in part of application No. 17/567,049, filed on Dec. 31, 2021, granted, now 11,329,059, issued on May 10, 2022.
Application 17/567,049 is a continuation in part of application No. 17/485,504, filed on Sep. 27, 2021, granted, now 11,251,149, issued on Feb. 15, 2022.
Application 17/485,504 is a continuation in part of application No. 17/372,476, filed on Jul. 11, 2021, granted, now 11,158,598, issued on Oct. 26, 2021.
Application 17/372,476 is a continuation in part of application No. 17/214,883, filed on Mar. 28, 2021, granted, now 11,107,803, issued on Aug. 31, 2021.
Application 17/214,883 is a continuation in part of application No. 16/337,665, granted, now 10,991,675, issued on Apr. 27, 2021, previously published as PCT/US2017/052359, filed on Sep. 19, 2017.
Claims priority of provisional application 62/517,152, filed on Jun. 8, 2017.
Claims priority of provisional application 62/471,963, filed on Mar. 16, 2017.
Claims priority of provisional application 62/440,720, filed on Dec. 30, 2016.
Claims priority of provisional application 62/406,376, filed on Oct. 10, 2016.
Prior Publication US 2023/0402098 A1, Dec. 14, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 11/408 (2006.01); G11C 16/08 (2006.01); H10B 80/00 (2023.01); H10B 43/35 (2023.01); H10B 12/00 (2023.01); H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01)
CPC G11C 16/0483 (2013.01) [G11C 11/4087 (2013.01); G11C 16/08 (2013.01); H10B 12/30 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 80/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, the device comprising:
a first level comprising a plurality of first memory arrays,
wherein said first level comprises a plurality of first transistors and a plurality of first metal layers;
a second level disposed on top of said first level,
wherein said second level comprises a plurality of second memory arrays;
a third level disposed on top of said second level,
wherein said third level comprises a plurality of third transistors and a plurality of third metal layers,
wherein said third level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonding regions and a plurality of metal to metal bonding regions,
wherein said first level comprises first filled holes,
wherein said second level comprises second filled holes, and
wherein said third level comprises a plurality of decoder circuits.