US 11,869,588 B2
Three-state programming of memory cells
Hernan A Castro, Shingle Springs, CA (US); Jeremy M. Hirst, Orangevale, CA (US); Shanky K. Jain, Folsom, CA (US); Richard K. Dodge, Santa Clara, CA (US); and William A. Melton, Shingle Springs, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 22, 2022, as Appl. No. 17/727,493.
Application 17/727,493 is a division of application No. 16/729,731, filed on Dec. 30, 2019, granted, now 11,315,633.
Prior Publication US 2022/0246210 A1, Aug. 4, 2022
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/15 (2013.01); G11C 2213/71 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method of operating memory, comprising:
programming a memory cell to one of three possible data states by:
applying a voltage pulse to the memory cell;
determining whether the memory cell snaps back in response to the applied first voltage pulse; and
applying a plurality of additional voltage pulses to the memory cell upon determining the memory cell does not snap back in response to the applied voltage pulse, wherein each of the plurality of additional voltage pulses has a same polarity as the voltage pulse pulse;
wherein the one of the three possible data states is associated with an asymmetric threshold voltage distribution whose magnitude is greater for a negative polarity than a positive polarity.