US 11,869,579 B2
Page buffer circuit and memory device including the same
Inho Kang, Yongin-si (KR); Ilhan Park, Suwon-si (KR); and Jinyoung Chun, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 19, 2021, as Appl. No. 17/530,911.
Claims priority of application No. 10-2021-0063169 (KR), filed on May 17, 2021.
Prior Publication US 2022/0366964 A1, Nov. 17, 2022
Int. Cl. G11C 11/4093 (2006.01); G11C 11/406 (2006.01); G11C 7/10 (2006.01); G11C 11/4096 (2006.01); G11C 11/4074 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4093 (2013.01) [G11C 7/1039 (2013.01); G11C 11/4074 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/40615 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A page buffer circuit comprising:
a plurality of page buffers connected to a plurality of bitlines,
wherein each of the plurality of page buffers comprises a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node,
wherein each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node, and
wherein each of the plurality of page buffers is configured to perform a first refresh operation and a second refresh operation to refresh the data stored in the storage node,
the first refresh operation stores inverted data that are inverted from the data in the storage node, and
the second refresh operation stores the data that are inverted from the inverted data in the storage node by using the charge sharing between the storage node and the sensing node.