US 11,869,568 B2
Memory device for performing smart refresh operation and memory system including the same
Byeong Yong Go, Gyeonggi-do (KR); Woongrae Kim, Gyeonggi-do (KR); and Yoonna Oh, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 3, 2022, as Appl. No. 17/591,982.
Claims priority of application No. 10-2021-0118434 (KR), filed on Sep. 6, 2021.
Prior Publication US 2023/0077248 A1, Mar. 9, 2023
Int. Cl. G11C 11/406 (2006.01); G11C 29/00 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/4096 (2013.01); G11C 29/72 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory bank comprising a first cell mat used as a normal area and a second cell mat used as a row hammer area and a redundancy area, each of the areas being an array of memory cells;
a target address generation circuit suitable for:
saving, in the row hammer area, a count of a received address for an active operation on the memory bank by performing an internal access operation on the row hammer area during the active operation, and
setting, a particular count which satisfies a preset condition, an address corresponding to the particular count as a target address;
a refresh control circuit suitable for controlling a smart refresh operation on the target address; and
a column repair circuit suitable for repairing, when a bit line of the normal area has a defect, the bit line of the normal area with a bit line of the redundancy area.