US 11,869,564 B2
Embedded ferroelectric memory cell
Tzu-Yu Chen, Kaohsiung (TW); Kuo-Chi Tu, Hsin-Chu (TW); Wen-Ting Chu, Kaohsiung (TW); and Yong-Shiuan Tsair, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 18, 2022, as Appl. No. 17/866,946.
Application 17/177,627 is a division of application No. 16/267,668, filed on Feb. 5, 2019, granted, now 10,930,333, issued on Feb. 23, 2021.
Application 17/866,946 is a continuation of application No. 17/177,627, filed on Feb. 17, 2021, granted, now 11,437,084.
Claims priority of provisional application 62/724,289, filed on Aug. 29, 2018.
Prior Publication US 2022/0351769 A1, Nov. 3, 2022
Int. Cl. G11C 11/22 (2006.01); H01L 29/51 (2006.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01)
CPC G11C 11/2259 (2013.01) [G11C 11/223 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); H01L 29/516 (2013.01); H10B 51/30 (2023.02); H10B 51/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip structure, comprising:
a first source/drain region and a second source/drain region disposed within a substrate;
a select gate disposed over the substrate between the first source/drain region and the second source/drain region;
a ferroelectric random-access memory (FeRAM) device disposed over the substrate between the select gate and the first source/drain region;
a first sidewall spacer comprising one or more dielectric materials arranged laterally between the select gate and the FeRAM device; and
an inter-level dielectric (ILD) structure laterally surrounding the FeRAM device and the select gate and vertically overlying a top surface of the first sidewall spacer.