CPC G11C 11/2259 (2013.01) [G11C 11/223 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); H01L 29/516 (2013.01); H10B 51/30 (2023.02); H10B 51/40 (2023.02)] | 20 Claims |
1. An integrated chip structure, comprising:
a first source/drain region and a second source/drain region disposed within a substrate;
a select gate disposed over the substrate between the first source/drain region and the second source/drain region;
a ferroelectric random-access memory (FeRAM) device disposed over the substrate between the select gate and the first source/drain region;
a first sidewall spacer comprising one or more dielectric materials arranged laterally between the select gate and the FeRAM device; and
an inter-level dielectric (ILD) structure laterally surrounding the FeRAM device and the select gate and vertically overlying a top surface of the first sidewall spacer.
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