US 11,869,116 B2
Line interleaving controller, image signal processor and application processor including the same
Kilhyung Cha, Seoul (KR); Jinsoo Park, Seoul (KR); Dongwoo Lee, Yongin-si (KR); Serhoon Lee, Yongin-si (KR); and Sungjin Huh, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 29, 2022, as Appl. No. 18/059,607.
Application 18/059,607 is a continuation of application No. 17/136,494, filed on Dec. 29, 2020, granted, now 11,514,552, issued on Nov. 29, 2022.
Claims priority of application No. 10-2020-0067473 (KR), filed on Jun. 4, 2020.
Prior Publication US 2023/0088614 A1, Mar. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 15/00 (2011.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06F 9/54 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 9/544 (2013.01); G06F 13/1647 (2013.01); G06F 13/4282 (2013.01); G06T 1/60 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system for processing image data, the system comprising:
a bus;
a plurality of imaging devices connected to the bus and configured to provide a plurality of image frames, each image frame including a plurality of image data lines;
a plurality of interfaces connected to the bus and configured to respectively receive the plurality of image frames through a plurality of channels;
a line interleaving controller configured to
receive the plurality of image data lines included in each image frame from each interface,
generate a number of virtual data lines corresponding to each image frame, and
output the plurality of image data lines and the virtual data lines; and
an image signal processor core including at least one pipeline circuit, the pipeline circuit including a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller, the image signal processor core configured to process one or more end image data lines included in an end portion of each image frame based on the virtual data lines.