US 11,869,113 B2
Systems and methods for exploiting queues and transitional storage for improved low-latency high-bandwidth on-die data retrieval
Aravindh Anantaraman, Folsom, CA (US); Altug Koker, El Dorado Hills, CA (US); Varghese George, Folsom, CA (US); Subramaniam Maiyuran, Gold River, CA (US); SungYe Kim, Folsom, CA (US); and Valentin Andrei, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 7, 2021, as Appl. No. 17/544,826.
Application 17/544,826 is a continuation of application No. 16/355,250, filed on Mar. 15, 2019, granted, now 11,227,358.
Prior Publication US 2022/0164917 A1, May 26, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01)
CPC G06T 1/20 (2013.01) [G06F 9/3802 (2013.01); G06F 9/3877 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics multiprocessor, comprising:
at least one processing engine to provide a request;
a queue or transitional buffer to function as cache memory and to provide on-die or on chip data retrieval for the graphics multiprocessor; and
logic on die or on chip with the queue or transitional buffer, the logic is configured to cause the request of the at least one processing engine to be transferred to the queue or transitional buffer for temporary storage instead of transferring the request to off chip memory when the queue or transitional buffer has a predetermined amount of storage capacity.