US 11,868,908 B2
Processor compiler for scheduling instructions to reduce execution delay due to dependencies
Jonathan Alexander Ross, Palo Alto, CA (US); and Gregory M. Thorson, Palo Alto, CA (US)
Assigned to Groq, Inc., Mountain View, CA (US)
Filed by Groq, Inc., Mountain View, CA (US)
Filed on Dec. 16, 2022, as Appl. No. 18/083,388.
Application 18/083,388 is a continuation of application No. 16/526,936, filed on Jul. 30, 2019, granted, now 11,568,275.
Application 16/526,936 is a continuation of application No. 16/132,102, filed on Sep. 14, 2018, granted, now 11,170,307, issued on Nov. 9, 2021.
Claims priority of provisional application 62/561,516, filed on Sep. 21, 2017.
Prior Publication US 2023/0121986 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 5/022 (2023.01); G06N 20/00 (2019.01)
CPC G06N 5/022 (2013.01) [G06N 20/00 (2019.01)] 10 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable storage medium comprising stored computer executable instructions, the computer executable instructions which when executed by a compiler operating on at least one computer processor, cause the at least one computer processor to:
access information describing at least a schedule of a plurality of instructions for execution at a processor and resources of the processor used to execute each instruction of the plurality of instructions;
determine an execution delay for each instruction of the plurality of instructions by the resources based on the accessed information, the determined execution delay including an amount of time before one or more operands of each instruction are ready to be used by the resources;
modify the schedule of the plurality of instructions for execution, such that a delay due to dependencies among multiple instructions of the plurality of instructions is reduced when the plurality of instructions are executed at the processor, the schedule indicating at least an order in which to execute the plurality of instructions; and
compile the plurality of instructions based on the modified schedule for execution at the processor.