CPC G06N 3/065 (2023.01) [G06N 3/04 (2013.01); G06N 3/08 (2013.01); G06N 3/084 (2013.01); G06N 3/105 (2013.01); H03K 19/0944 (2013.01)] | 18 Claims |
1. An integrated circuit, comprising:
a multi-layered neural network disposed in an analog multiplier array of a plurality of two-quadrant multipliers arranged in a memory sector of the integrated circuit, wherein at least one of the plurality of two-quadrant multipliers is a bias-free two-quadrant multiplier,
wherein each multiplier of the multipliers is wired to ground and draws a reduced amount of current when input signal values for input signals to transistors of the multiplier are near zero or zero, weight values of the transistors of the multiplier are near zero or zero, or a combination thereof, and
wherein each bias-free two-quadrant multiplier of the two-quadrant multipliers has a differential structure configured to allow programmatic compensation for overshoot if any one of two cells is set with a higher weight value than targeted.
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