US 11,868,876 B2
Systems and methods for sparsity exploiting
Kurt F. Busch, Laguna Hills, CA (US); Jeremiah H. Holleman, III, Davidson, NC (US); Pieter Vorenkamp, Laguna Beach, CA (US); and Stephen W. Bailey, Irvine, CA (US)
Assigned to Syntiant, Irvine, CA (US)
Filed by SYNTIANT, Irvine, CA (US)
Filed on Jan. 21, 2022, as Appl. No. 17/581,453.
Application 17/581,453 is a continuation of application No. 16/041,565, filed on Jul. 20, 2018, granted, now 11,232,349.
Claims priority of provisional application 62/535,705, filed on Jul. 21, 2017.
Prior Publication US 2022/0147807 A1, May 12, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/065 (2023.01); G06N 3/084 (2023.01); G06N 3/04 (2023.01); G06N 3/08 (2023.01); G06N 3/10 (2006.01); H03K 19/0944 (2006.01)
CPC G06N 3/065 (2023.01) [G06N 3/04 (2013.01); G06N 3/08 (2013.01); G06N 3/084 (2013.01); G06N 3/105 (2013.01); H03K 19/0944 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a multi-layered neural network disposed in an analog multiplier array of a plurality of two-quadrant multipliers arranged in a memory sector of the integrated circuit, wherein at least one of the plurality of two-quadrant multipliers is a bias-free two-quadrant multiplier,
wherein each multiplier of the multipliers is wired to ground and draws a reduced amount of current when input signal values for input signals to transistors of the multiplier are near zero or zero, weight values of the transistors of the multiplier are near zero or zero, or a combination thereof, and
wherein each bias-free two-quadrant multiplier of the two-quadrant multipliers has a differential structure configured to allow programmatic compensation for overshoot if any one of two cells is set with a higher weight value than targeted.