| CPC G06F 9/4881 (2013.01) [G06F 5/01 (2013.01); G06F 9/3802 (2013.01); G06F 9/3856 (2023.08); G06F 9/3885 (2013.01)] | 20 Claims |
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1. A processor, comprising:
one or more computational arrays each comprising an array of computational elements arranged in a plurality of columns, each computational element adapted to perform a function on received data;
an instruction dispatch circuit configured to provide instructions to the computational elements of the one or more computational arrays, comprising:
an instruction buffer memory configured to receive input instructions, the instruction buffer memory further comprising a plurality of memory output locations connected to respective columns of the one or more computational arrays; and
an instruction dispatch unit (IDU) configured to process the input instructions received by the instruction buffer memory to generate a plurality of instructions and output each of the plurality of instructions to respective memory output locations of the instruction memory buffer, based upon which column of computational elements of the one or more computational arrays each instruction is to be received at,
wherein computational elements of the one or more computational arrays execute instructions of the plurality of instructions from the plurality of memory output locations on the received data, based upon a timing at which the instructions reaches each computational element.
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