US 11,868,786 B1
Systems and methods for distributed and parallelized emulation processor configuration
Ngai Ngai William Hung, San Jose, CA (US); and Amiya Ranjan Satapathy, San Jose, CA (US)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Jan. 14, 2022, as Appl. No. 17/576,808.
Int. Cl. G06F 9/44 (2018.01); G06F 9/445 (2018.01); G06F 9/4401 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/44505 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 9/30189 (2013.01); G06F 9/4403 (2013.01); G06F 9/4401 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of accelerated modification of an emulation processor system, comprising:
loading, a portion of data to a memory of a first emulation processor, wherein the data contains information about a list of sequential updates to one or more hardware states of the first emulation processor and an embedded controller in the first emulation processor which takes the above data and performs corresponding updates to remaining states or registers of the first emulation processor;
loading, in parallel, a second portion of the data to a memory of a second emulation processor operatively coupled with the first emulation processor, wherein the data contains information about a list of sequential updates to the hardware states of the second emulation processor, and an embedded controller in the second emulation processor which takes the second portion of the data and performs the corresponding updates to remaining states or registers of the second emulation processor; and
loading, in parallel, a third portion of the data to the memory of other emulation processors of the emulation processor system that contains embedded controllers performing their own state updates.