US 11,868,773 B2
Inferring future value for speculative branch resolution in a microprocessor
Steven J. Battle, Philadelphia, PA (US); Brian D. Barrick, Pflugerville, TX (US); Dung Q. Nguyen, Austin, TX (US); Richard J. Eickemeyer, Rochester, MN (US); John B. Griswell, Jr., Austin, TX (US); Balaram Sinharoy, Lagrangeville, NY (US); Brian W. Thompto, Austin, TX (US); and Tu-An T. Nguyen, Austin, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jan. 6, 2022, as Appl. No. 17/569,951.
Prior Publication US 2023/0214218 A1, Jul. 6, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30058 (2013.01) [G06F 9/30021 (2013.01); G06F 9/30043 (2013.01); G06F 9/3842 (2013.01); G06F 9/3856 (2023.08)] 20 Claims
OG exemplary drawing
 
1. A method for processing instructions in a processor, the method comprising:
storing, in response to a load bit of a first instruction of a compare immediate-conditional branch instruction sequence being set, information from the first instruction into a compare register, including an ITAG of the first instruction;
writing, in response to the load bit of the first instruction being set, an immediate field of a compare immediate instruction of the compare immediate-conditional branch instruction sequence into the compare register;
writing, in response to detecting a conditional branch instruction of the compare immediate-conditional branch instruction sequence, an inferred compare result value into the compare register;
auto-finishing the compare immediate and the conditional branch instructions from the compare immediate-conditional branch instruction sequence without executing the compare immediate and the conditional branch instruction in an execution unit;
comparing, in response to executing the first instruction, a writeback ITAG of the first instruction to the ITAG of the first instruction stored in the compare register;
writing, in response to the writeback ITAG of the first instruction matching the ITAG of the first instruction stored in the compare register, a first instruction writeback result into a data field in the compare register;
comparing, in response to the first instruction writeback result being written into the data field in the compare register, the first instruction writeback result written into the data field in the compare register with the immediate field of the compare immediate instruction written into the compare register to generate a computed compare result value;
comparing the computed compare result value to the inferred compare result value;
flushing, in response to the computed compare result value not matching the inferred compare result value, instructions in the processor; and
not flushing, in response to the computed compare result value matching the inferred compare result value, instructions in the processor.