US 11,868,741 B2
Processing element, neural processing device including same, and multiplication operation method using same
Jaewan Bae, Seongnam-si (KR); Jinwook Oh, Seongnam-si (KR); and Karim Charfi, Seongnam-si (KR)
Assigned to Rebellions Inc., Seongnam-si (KR)
Filed by Rebellions Inc., Seongnam-si (KR)
Filed on Jun. 15, 2022, as Appl. No. 17/807,082.
Claims priority of application No. 10-2021-0078867 (KR), filed on Jun. 17, 2021; and application No. 10-2022-0066221 (KR), filed on May 30, 2022.
Prior Publication US 2022/0405560 A1, Dec. 22, 2022
Int. Cl. G06F 7/533 (2006.01); G06N 3/063 (2023.01); G06F 7/50 (2006.01); G06F 7/535 (2006.01); G06F 7/544 (2006.01)
CPC G06F 7/533 (2013.01) [G06F 7/50 (2013.01); G06F 7/535 (2013.01); G06F 7/5443 (2013.01); G06N 3/063 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A processing element, included in a neural processor, the processing element, comprises:
a weight register configured to store a weight;
an input activation register configured to store input activation;
a flexible multiplier, comprising:
a first multiplier of a first precision;
a second multiplier of the first precision; and
digit aligning circuit, configured to generate result data by performing a multiplication operation of the weight and the input activation by using the first multiplier or using both the first multiplier and the second multiplier in response to a calculation mode signal,
wherein the first multiplier generates a first partial multiplication group using the multiplication operation of the weight and the input activation wherein the first partial multiplication has a first digit, the second multiplier generates a second partial multiplication group using the multiplication operation of the weight and the input activation wherein the second partial multiplication has a second digit different from the first digit, the second multiplier generates a third partial multiplication group that has the first digit, and the digit aligning circuit generates a first aligned partial multiplication group including the first partial multiplication group and the third partial multiplication group and a second aligned partial multiplication group including the second partial multiplication group when the calculation mode is a first mode signal associated with a second precision greater than the first precision; and
a saturating adder configured to generate a partial sum by using the result data.