US 11,868,694 B1
System and method for optimizing emulation throughput by selective application of a clock pattern
Bojan Mihajlovic, Marlborough, MA (US); Alexander Rabinovitch, Marlborough, MA (US); and Fei Chen, Marlborough, MA (US)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on May 14, 2020, as Appl. No. 16/874,197.
Claims priority of provisional application 62/847,418, filed on May 14, 2019.
Int. Cl. G06F 30/3312 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 2119/12 (2020.01)] 18 Claims
OG exemplary drawing
 
1. A system, comprising:
a host system comprising:
a memory; and
a processor configured to perform operations stored in the memory, wherein the processor executes the operations to:
analyze each of a first set of sequential elements of a plurality of sequential elements to determine an edge of a clock signal pattern of a clock associated with each of the first set of sequential elements causing an output change at corresponding one or more sequential elements of the first set of sequential elements;
discard one or more cycles of the clock signal pattern of the clock from emulation that do not include the edge of the clock signal pattern that causes at least one sequential element of the first set of sequential elements to change an output; and
replicate a clock tree to generate a replicated clock tree, wherein the clock tree and the replicated clock tree are fed adjacent cycles of the clock signal pattern of the clock.