US 11,868,693 B2
Verification performance profiling with selective data reduction
Rohit Kumar Jain, Milpitas, CA (US); David Lowder, Molalla, OR (US); James Insley, Dundee, OR (US); and Srinivasa Cherukumilli, San Ramon, CA (US)
Assigned to Siemens Industry Software Inc., Plano, TX (US)
Filed by Siemens Industry Software Inc., Plano, TX (US)
Filed on Apr. 21, 2021, as Appl. No. 17/236,606.
Prior Publication US 2022/0343044 A1, Oct. 27, 2022
Int. Cl. G06F 30/33 (2020.01); G06F 16/23 (2019.01); G06F 111/02 (2020.01)
CPC G06F 30/33 (2020.01) [G06F 16/2379 (2019.01); G06F 2111/02 (2020.01)] 17 Claims
OG exemplary drawing
 
1. A method comprising:
collecting, by a computing system, samples of performance data during functional verification of a circuit design describing an electronic device;
generating, by the computing system, a profile presentation based on the samples of performance data, wherein the profile presentation, when displayed, is configured to annunciate portions of the circuit design corresponding to at least one performance hotspot, wherein generating the profile presentation further comprises:
identifying design elements in each of the samples of the performance data; and
building a hierarchical tree or flat representations for each type of the identified design elements, wherein each of the hierarchical trees or flat representations includes counter values associated with a presence of the design elements in the samples of the performance data;
receiving, by the computing system, a data reduction request based on the performance hotspot annunciated by the profile presentation, wherein the data reduction request is configured to identify a subset of the performance data in the profile presentation; and
generating, by the computing system, a refined profile presentation based, at least in part, on the samples of performance data and the subset of the performance data identified in the data reduction request.