US 11,868,692 B2
Address generators for verifying integrated circuit hardware designs for cache memory
Anthony Wood, Bristol (GB); and Philip Chambers, Bristol (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Apr. 2, 2021, as Appl. No. 17/221,535.
Application 17/221,535 is a continuation of application No. 16/855,130, filed on Apr. 22, 2020, granted, now 10,990,726.
Application 16/855,130 is a continuation of application No. 15/914,072, filed on Mar. 7, 2018, granted, now 10,671,699, issued on Jun. 2, 2020.
Claims priority of application No. 1703646 (GB), filed on Mar. 7, 2017.
Prior Publication US 2021/0224450 A1, Jul. 22, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/33 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 12/00 (2006.01); G11C 29/54 (2006.01); G06F 12/0817 (2016.01); G06F 12/0864 (2016.01); G06F 117/08 (2020.01)
CPC G06F 30/33 (2020.01) [G06F 12/082 (2013.01); G06F 30/3308 (2020.01); G11C 29/54 (2013.01); G06F 12/0864 (2013.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 2117/08 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A system to verify an integrated circuit hardware design for an n-way set associative cache, the n-way set associative cache configured to store a subset of data stored in a main memory, the system comprising:
one or more processors; and
memory comprising computer executable instructions that when executed by the one or more processors cause the one or more processors to implement:
an address generator configured to:
receive an address request;
in response to receiving the address request, select an address from a list of cache set addresses, the list of cache set addresses comprising one or more addresses of the main memory corresponding to each of one or more target sets; and
provide the selected address to a driver to apply stimulus to an instantiation of the integrated circuit hardware design for the n-way set associative cache based on the received address.