US 11,868,619 B2
Partial array refresh timing
Liji Gopalakrishnan, Sunnyvale, CA (US); Thomas Vogelsang, Mountain View, CA (US); and John Eric Linstadt, Palo Alto, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Appl. No. 17/785,269
Filed by Rambus Inc., San Jose, CA (US)
PCT Filed Dec. 3, 2020, PCT No. PCT/US2020/063135
§ 371(c)(1), (2) Date Jun. 14, 2022,
PCT Pub. No. WO2021/126541, PCT Pub. Date Jun. 24, 2021.
Claims priority of provisional application 62/951,953, filed on Dec. 20, 2019.
Prior Publication US 2023/0026876 A1, Jan. 26, 2023
Int. Cl. G06F 3/06 (2006.01); G11C 11/406 (2006.01); G06F 13/16 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 11/40622 (2013.01); G06F 13/1636 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a command interface to transmit at least a first refresh command and a first next subsequent command to a memory component; and,
refresh control circuitry to, based at least on a first refresh masking configuration of the memory component and a first row refresh scheme of the memory component, select a first Row Refresh Cycle Timing (tRFC) to determine a first time interval between a transmission of the first refresh command and the first next subsequent command.