US 11,868,512 B2
Detection of a netlist version in a security chip
Scott C. Best, Palo Alto, CA (US); and Christopher Leigh Rodgers, Hillsborough, CA (US)
Assigned to CRYPTOGRAPHY RESEARCH, INC., San Jose, CA (US)
Appl. No. 17/636,831
Filed by CRYPTOGRAPHY RESEARCH, INC., San Jose, CA (US)
PCT Filed Sep. 4, 2020, PCT No. PCT/US2020/049505
§ 371(c)(1), (2) Date Feb. 18, 2022,
PCT Pub. No. WO2021/046420, PCT Pub. Date Mar. 11, 2021.
Claims priority of provisional application 62/897,177, filed on Sep. 6, 2019.
Prior Publication US 2022/0269827 A1, Aug. 25, 2022
Int. Cl. G06F 21/40 (2013.01); G06F 21/76 (2013.01)
CPC G06F 21/76 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a pattern detector circuit in a security chip, wherein the pattern detector circuit monitors accesses of a plurality of configuration registers, each of the plurality of configuration registers having a corresponding address;
in response to receiving from a host a predefined sequence of accesses of the plurality of configuration registers for one or more operations to the plurality of configuration registers, determining, by a processing circuit in the pattern detector circuit, a value indicative of a current version of a netlist for the security chip; and
making the determined value available to be obtained by a read operation by the host at a specific configuration register address.