US 11,868,488 B2
Memory devices with cryptographic components
Antonino Mondello, Messina (IT); Carmelo Condemi, San Giovanni la Punta (IT); Francesco Tomaiuolo, Acireale (IT); and Tommaso Zerilli, Mascalucia (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 28, 2022, as Appl. No. 17/994,680.
Application 17/994,680 is a continuation of application No. 16/255,142, filed on Jan. 23, 2019, granted, now 11,514,174.
Prior Publication US 2023/0086754 A1, Mar. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/30 (2006.01); G06F 12/14 (2006.01); G06F 21/60 (2013.01); H04L 9/32 (2006.01); H03M 13/29 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G06F 21/64 (2013.01); G06F 21/79 (2013.01)
CPC G06F 21/602 (2013.01) [G06F 11/1068 (2013.01); G06F 21/64 (2013.01); G06F 21/79 (2013.01); G11C 29/52 (2013.01); H03M 13/2906 (2013.01); H04L 9/3242 (2013.01); H04L 9/3278 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first controller comprising a first error correction code component; and
a memory device coupled to the first controller, the memory device comprising:
an array of memory cells;
a second error correction code component coupled to the array and configured to correct data read from the array;
a cryptographic component configured to receive, from the second error correction code component, the corrected data read from the array; and
a command interface coupled to a second controller and configured to activate the second controller in response to receiving a command from the first controller.