CPC G06F 21/602 (2013.01) [G06F 11/1068 (2013.01); G06F 21/64 (2013.01); G06F 21/79 (2013.01); G11C 29/52 (2013.01); H03M 13/2906 (2013.01); H04L 9/3242 (2013.01); H04L 9/3278 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a first controller comprising a first error correction code component; and
a memory device coupled to the first controller, the memory device comprising:
an array of memory cells;
a second error correction code component coupled to the array and configured to correct data read from the array;
a cryptographic component configured to receive, from the second error correction code component, the corrected data read from the array; and
a command interface coupled to a second controller and configured to activate the second controller in response to receiving a command from the first controller.
|