CPC G06F 15/7821 (2013.01) | 20 Claims |
1. An apparatus comprising:
a plurality of storage devices configured to store data in response to program requests received from an external processor; and
a processing-in-memory (PIM) circuit configured to process PIM commands in response to kernel instructions received from the external processor, wherein an instruction set architecture (ISA) implemented by the PIM circuit has fewer instructions than an ISA implemented by the external processor, and wherein processing resources of the PIM circuit are configured to be virtualized such that the PIM circuit is configured to concurrently process PIM commands from multiple PIM kernels.
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