US 11,868,297 B2
Far-end data migration device and method based on FPGA cloud platform
Jiangwei Wang, Jiangsu (CN); Rui Hao, Jiangsu (CN); and Hongwei Kan, Jiangsu (CN)
Assigned to INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
Appl. No. 17/792,265
Filed by INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
PCT Filed Aug. 25, 2020, PCT No. PCT/CN2020/111006
§ 371(c)(1), (2) Date Jul. 12, 2022,
PCT Pub. No. WO2021/143135, PCT Pub. Date Jul. 22, 2021.
Claims priority of application No. 202010031268.7 (CN), filed on Jan. 13, 2020.
Prior Publication US 2023/0045601 A1, Feb. 9, 2023
Int. Cl. G06F 13/40 (2006.01); G06F 15/173 (2006.01); H04L 67/1097 (2022.01)
CPC G06F 13/4022 (2013.01) [G06F 15/17331 (2013.01); H04L 67/1097 (2013.01); G06F 2213/0026 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A far-end data migration device based on a Field Programmable Gate Array (FPGA) cloud platform, comprising a server, a switch, and a plurality of FPGA acceleration cards, wherein the server transmits data to be accelerated to the plurality of FPGA acceleration cards by means of the switch; and the plurality of FPGA acceleration cards are configured to perform at least one of a primary acceleration or a secondary acceleration on the data to yield accelerated data, and are configured to migrate the accelerated data;
wherein each of the plurality of FPGA acceleration cards comprises a SHELL and a FPGA Accelerator Unit (FAU), wherein the SHELL is configured as an interface connection between the FPGA acceleration card and the switch, and is configured to migrate the data on the FPGA acceleration card; and the FAU is configured to perform the at least one of the primary acceleration or the secondary acceleration on the data on the FPGA acceleration cart;
the SHELL comprises an iRDMA, a Memory, a Peripheral Component Interconnect Express (PCIE), and a Media Access Control (MAC), wherein the Memory is connected with the iRDMA; the iRDMA is connected with the PCIE and the MAC; in response to data in the Memory on the FPGA acceleration card being accelerated by the FAU, the iRDMA is configured to implement data migration between the Memory and the FAU on the FPGA acceleration card; and in response to the accelerated data being migrated on the plurality of FPGA acceleration cards, the iRDMA implements data migration between the Memories on the plurality of FPGA acceleration cards through MAC interfaces.