US 11,868,296 B2
High bandwidth core to network-on-chip interface
Himanshu Kaul, Portland, OR (US); Mark A. Anders, Hillsboro, OR (US); and Gregory K. Chen, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 22, 2022, as Appl. No. 17/701,593.
Application 17/701,593 is a continuation of application No. 14/574,352, filed on Dec. 17, 2014, granted, now 11,321,263.
Prior Publication US 2022/0214988 A1, Jul. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H05K 7/10 (2006.01); G06F 13/40 (2006.01); H04L 49/10 (2022.01); H04L 12/54 (2022.01)
CPC G06F 13/4022 (2013.01) [H04L 12/54 (2013.01); H04L 49/10 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A processor comprising:
a core; and
a router comprising:
a first port set comprising:
an input port to receive first circuit-switched data from the core; and
an output port to provide second circuit-switched data to the core;
a first set of signal lines dedicated to communicate circuit-switched data between a second port set of the router and the output port of the first port set;
a second set of signal lines dedicated to communicate circuit-switched data between a third port set of the router and the output port of the first port set;
a third set of signal lines dedicated to communicate circuit-switched data between the second port set and the input port of the first port set; and
a fourth set of signal lines dedicated to communicate circuit-switched data between the third port set and the input port of the first port set;
wherein the first circuit-switched data comprises first data communicated to the second port set and second data communicated to the third port set, wherein the first data is different from the second data and is communicated simultaneously with the second data.