US 11,868,276 B2
Non-volatile memory write access control
Richard A Bramley, Mansfield, MA (US); Baraneedharan Anbazhagan, Spring, TX (US); and Valiuddin Ali, Spring, TX (US)
Assigned to HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., Spring, TX (US)
Filed by HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., Spring, TX (US)
Filed on Jun. 2, 2022, as Appl. No. 17/830,730.
Prior Publication US 2023/0393993 A1, Dec. 7, 2023
Int. Cl. G06F 12/14 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/1416 (2013.01) [G06F 12/0246 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/7207 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A computing device comprising:
a non-volatile memory;
a communication interface connected to the non-volatile memory to control access to the non-volatile memory; and
a processor connected to the communication interface, wherein the processor is to:
upon booting of the computing device, disable write access to the non-volatile memory via the communication interface;
in response to a trigger of a system management mode (SMM), verify all processor threads have been pulled into the SMM;
in response to a successful verification, enable write access to the non-volatile memory via the communication interface; and
upon exiting the SMM, disable write access to the non-volatile memory via the communication interface.