US 11,868,258 B2
Scalable cache coherency protocol
James Vash, San Ramon, CA (US); Gaurav Garg, San Jose, CA (US); Brian P. Lilly, San Francisco, CA (US); Ramesh B. Gunna, San Jose, CA (US); Steven R. Hutsell, San Jose, CA (US); Lital Levy-Rubin, Tel Aviv (IL); Per H. Hammarlund, Sunnyvale, CA (US); and Harshavardhan Kaushikkar, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 27, 2023, as Appl. No. 18/160,575.
Application 18/160,575 is a continuation of application No. 18/058,105, filed on Nov. 22, 2022.
Application 18/058,105 is a continuation of application No. 17/315,725, filed on May 10, 2021, granted, now 11,544,193, issued on Jan. 3, 2023.
Claims priority of provisional application 63/077,371, filed on Sep. 11, 2020.
Prior Publication US 2023/0169003 A1, Jun. 1, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0815 (2016.01); G06F 12/0831 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 12/0831 (2013.01); G06F 2212/1032 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of coherent agent circuits, wherein a given agent circuit of the plurality of coherent agent circuits comprises one or more caches to cache memory data; and
a directory configured to track at least: (i) which of the plurality of coherent agent circuits is caching copies of a plurality of cache blocks in a memory in the system, and (ii) states of the cached copies in the plurality of coherent agent circuits;
a coherency controller circuit coupled to the directory, wherein based on a first request for a first cache block by a first agent circuit of the plurality of coherent agent circuits, the coherency controller circuit is configured to:
read an entry corresponding to the first cache block from the directory, and
issue a message to a second agent circuit of the plurality of coherent agent circuits that has a cached copy of the first cache block according to the entry, wherein the message requests a state change in the state of the cached copy in the second agent circuit, and
include an identifier of a first state of the first cache block in the second agent circuit in the message; and
wherein, based on the message, the second agent circuit is configured to:
compare the first state to a second state of the first cache block in the second agent circuit, and
delay processing of the state change based on the first state not matching the second state until the second state is changed to the first state.